1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to an improvement in a wiring formation step performed during the manufacturing of a semiconductor device.
2. Description of the Prior Art
In recent years, the degree of integration of semiconductor integrated circuits has been increased significantly, and this trend is expected to continue in the future. This high degree of integration is achieved by micropatterning and by the high packing density of elements. A multilayer wiring technique is widely used to achieve micropatterning and high packing density.
With regard to the multilayer wiring technique, the following three conditions must be observed.
First, the resistance of the wiring must be low.
Second, an interlayer insulating film interposed between wiring layers must be able to be planarized easily.
Third, wiring layers must be able to be connected easily.
With these conditions in mind, various multilayer wiring techniques have been investigated. However, due to a variety of problems encountered during the actual manufacturing steps, no technique has yet been found for producing a multilayer wiring structure, which satisfies all the above conditions.
FIG. 1 is a sectional view showing an example of a normal multilayer wiring structure in a conventional semiconductor device. In FIG. 1, reference numeral 11 denotes a p-type silicon substrate. Various n+-type impurity regions for constituting elements--e.g., transistors--required in an integrated circuit, are formed in substrate 11. First layer wiring 12 composed of a polycrystalline silicon film is formed on substrate 11, and an insulating film is interposed between wiring 12 and substrate 11. Wiring 12 is covered with interlayer insulating film 13 composed of SiO.sub.2. Second layer wiring 14, composed of a metal such as Al, is formed on film 13. Wiring 14 is connected to wiring 12 and substrate 11 via contact holes formed in film 13. This multilayer wiring structure results from forming wiring 12 first, then depositing film 13, forming the contact holes, and then depositing and patterning a second layer wiring material.
The above conventional multilayer wiring structure does, however, have the following drawbacks:
Al or an Al alloy, which is normally used as a wiring material of wiring 14, has a low melting point. For this reason, when wiring 14 is to be formed, using this material, gettering accompanied by high-temperature annealing cannot be sufficiently performed because the wiring 14 is melted. In addition, when wiring 14 is to be covered with an insulating film, a high-temperature melting step cannot be used for planarizing the insulating film. For this reason, in order to planarize the insulating film, a complex step such as an etch-back method or a lift-off method must be performed instead.
Otherwise, when polycrystalline silicon or a silicide of a refractory metal which has high melting point is used as the material of wiring 14, high-temperature annealing can be performed without any trouble. However, the wiring resistance is then increased to several tens to several hundred times that achieved when aluminum is used. For this reason, signal delay occurs between semiconductor elements, thereby posing a serious problem with regard to circuit design.
On the other hand, refractory metals such as molibdenum or tungsten have high melting points and low resistances. Therefore, when such a refractory metal is used as a second layer wiring material, it is assumed that the first and second conditions are satisfied. However, in this case also, when a heating step such as high-temperature melting is performed for gettering or planarizing, the wiring resistance is increased significantly. The reason for this is as follows:
As is shown in FIG. 1, layer 14 made of a refractory metal is in contact with polycrystalline silicon wiring 12 and silicon substrate 11. Therefore, when high-temperature annealing is performed, wiring 14 reacts with wiring 12 and substrate 11 at a contact portion therebetween, thereby being converted to silicide of the refractory metal. Although a process for preventing the formation of such a silicide is known, according to such a process, the wiring structure becomes complex and the number of necessary contact holes to connect the wires is increased. For this reason, micropatterning of elements is prevented, and the above-mentioned third conditions cannot be satisfied.
As has been described above, according to the conventional multilayer wiring technique, regardless of the wiring materials selected, the above three conditions required for a multilayer-wiring technique cannot be satisfied at the same time.